1. Field of the Invention
The invention relates to information processing technologies, and in particular, to an information processing apparatus having a plurality of processor units, a method of signal transmission of the information processing apparatus, and a bridge unit to be implemented therein.
2. Description of the Related Art
Recently, computers have become more diversified in function, and accordingly, devices to be connected to such computers have also been growing in variety. These devices exchange signals with the CPUs of the computers via buses. Bus bridges are used to connect a bus that are directly connected with the CPUs, to a bus that provide ports for device connection, thereby ensuring compatibility between the different types of buses. In addition, bus bridges can be hierarchically connected to form a device tree of buses of identical type, thereby increasing the number of ports available for device connection.
Meanwhile, information processing apparatuses having a multiprocessor architecture with a plurality of processors or a multihost architecture with a plurality of processor units have been commonly used in recent years to address the demand for faster processing speeds. These parallel processing technologies achieve processing speedup by distributing the processing of a single application over a plurality of processors or a plurality of hosts. An example of the structure of a multihost architecture is a fat tree structure (for example, see C.E. Leiserson “Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing” IEEE Transactions on Computer, Vol. 34, No. 10, pp. 892-901, 1985).
Take, for example, the case of an information processing apparatus that has a multihost architecture. When one application is distributed over a plurality of processor units for processing, access between the device trees can be complicated since the processor units manage different respective buses. Increasing the number of processor units to achieve speedup causes more complex processing of signal transmission and reception between the processor units, thus increasing access times.
Related Art List
C.E. Leiserson “Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing” IEEE Transactions on Computer, Vol. 34, No. 10, pp. 892-901, 1985